The present invention relates to a semiconductor integrated circuit device which matches the trend toward further miniaturization and to a method for designing the same.
If a plurality of functional blocks are formed in one chip, it has not been performed conventionally to provide MOS transistors contained in a plurality of digital functional circuit blocks with different gate lengths or provide the respective gate oxide films of the MOS transistors with different thicknesses.
Briefly, in a conventional circuit designing method, on-chip micro-patterning is regulated by one design rule and a reduction in margin resulting from patterning variations is compensated for by using a uniform value. The reason for a uniform margin allowed is that a difference of one order of magnitude or more exists between a required performance value and a required margin. In an exemplary case, a specification for a required access time is 3.0 ns, a mean value of actually obtained access times is 2.5 ns, and a required margin considering patterning variations is 0.3 ns. In the case where the specification for the required access time is set to 0.4 ns, however, if the mean value of actually obtained access times is improved to 0.25 ns and a margin of 0.30 ns is allowed, the improvement in performance is suppressed by the margin for patterning variations.
This indicates that, as increasingly higher performance is required in future, if a uniform margin for patterning variations is provided throughout the entire chip, an improvement in performance is suppressed by the uniform margin.
In other words, it becomes difficult to satisfy required performance throughout the entire chip, though the required performance is satisfied locally in a portion of the chip. As a result, the performance of the chip is limited by the worst portion of the entire chip so that the performance is not improved.
In an analog circuit or a circuit for which consideration should be given to a latch-up caused by an electrostatic damage (ESD) or to a breakdown voltage, it has been a conventional practice to use different design rules for a transistor provided on the I/O pad portion of the circuit and for the logic portion of the circuit. This is because different power supply voltages are applied thereto.
Thus, it has not been performed conventionally to use different design rules in one digital circuit block or in one analog circuit. It has not been performed, either, to divide one wafer into chips of different sizes or fabricate, from one wafer, various chips designed to have different functions or performances on a per chip basis.
As design sizes are reduced increasingly year after year, the design of a chip performed by applying one design rule to one chip encounters the following problems.
The design rule which is 0.13 xcexcm in the year 2001 is expected to become 0.10 xcexcm in the year 2005. If design is to be performed in accordance with the design rule of 0.10 xcexcm, a fabrication process requires a patterning accuracy on the order of several tens of nanometers.
In that case, it will become extremely difficult to control variations in patterning accuracy to several tens of nanometers in consideration of each of variations in patterning accuracy in the fabrication process depending on the regions of the principal surface (portion) of a wafer, the relationship between the regions (portions) of one chip and layout densities therein, and the like.
If design rules also considering variations in patterning accuracy are applied, a design margin is reduced dramatically so that the yield rate is reduced significantly. As a consequence, the trend toward further miniaturization drastically increases the manufacturing cost for a chip.
In view of the foregoing problems expected, an object of the present invention is to positively match the trend toward a further reduction in design size.
As a result of examining a performance required of each of a plurality of functional blocks integrated in one chip, the present inventor has concluded that an operating speed, a leakage current, and the like need not necessarily be the same for each of the functional blocks. In a system LSI using a design rule of 0.10 xcexcm or less which implements ultraminiaturization technology, in particular, all devices required for the system LSI are integrated with each other so that the trend toward the use of a different operating speed, a different leakage current, and the like for each of functional blocks will probably grow.
To attain the object, the present invention provides a semiconductor integrated circuit device which is constructed such that:
(1) if different finished sizes resulting from geometric features are predictable for design patterns containing elements and wires formed on one chip,
(2) if finished sizes are different depending on electric specifications required of the design patterns and on designing means (methods) for implementing the electric specifications, or
(3) if required specifications are different depending on usage modes in the design patterns, performance variations resulting from patterning variations and variations in required performance are complemented by each other. It follows therefore that circuit elements or wires in a semiconductor integrated circuit device formed on one substrate have a plurality of minimum sizes values.
Specifically, a first semiconductor integrated circuit device according to the present invention comprises: a plurality of design patterns composed of circuit elements or wires formed on a substrate, respective finished sizes of the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on a geometric feature of each of the design patterns.
In the first semiconductor integrated circuit device, design margins for the plurality of design patterns are not uniform so that an improvement in the performance of the device is not suppressed by a margin for patterning variations.
Preferably, in the first semiconductor integrated circuit device, the plurality of minimum size values are set for a length or width of each of parts composing the circuit elements, a spacing between the parts, an overlapping portion between the parts, or a configuration of a protruding portion of the part and are set for a width of each of the wires or a spacing between the wires.
Preferably, in the first semiconductor integrated circuit device, the circuit elements are bit cells in a memory device and an area occupied by each of the bit cells is determined by any of the plurality of minimum size values.
Preferably, in the first semiconductor integrated circuit device, the circuit elements are contained in an element formation layer and the wires are contained in a wiring layer, the device further comprising: one or more contacts for providing an electric connection between the element formation layer and the wiring layer, the minimum size value of the finished size of each of the contacts depending on an area occupied by the contact on the substrate or on the number of the contacts.
Preferably, in the first semiconductor integrated circuit device, the geometric feature is respective directions or positions of the circuit elements or the wires on the substrate and the plurality of minimum size values are set to correct dependence of the finished sizes on the directions or positions on the substrate.
Preferably, in the first semiconductor integrated circuit device, the geometric feature is a layout density of the circuit elements or the wires on the substrate and the plurality of minimum size values are set to correct dependence of the finished sizes on the layout density.
Preferably, in the first semiconductor integrated circuit device, the circuit elements are bit cells in a memory device, the geometric feature is a layout type of the bit cells, and the plurality of minimum size values are set to correct dependence of the finished size on a relationship between a direction in which a gate of a drive transistor extends and a direction in which a gate of an access transistor connected to a word line extends in each of the bit cells.
Preferably, in the first semiconductor integrated circuit device, the geometric feature is the presence or absence of a dummy pattern which is a dummy of each of the design patterns contained therein and, if the dummy patterns are contained in the design pattern, the plurality of minimum size values are set to correct dependence of the finished size on the dummy pattern.
A second semiconductor integrated circuit device according to the present invention comprises: a plurality of design patterns composed of circuit elements or wires formed on a substrate, the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on different finished sizes resulting from an electric specification of each of the design patterns and a designing means for implementing the electric specification.
In the second semiconductor integrated circuit device, design margins for the plurality of design patterns are not uniform so that an improvement in the performance of the device is not suppressed by a margin for patterning variations.
Preferably, in the second semiconductor integrated circuit device, the plurality of minimum size values are set for a length or width of each of parts composing the circuit elements, a spacing between the parts, an overlapping portion between the parts, or a configuration of a protruding portion of the part and are set for a width of each of the wires or a spacing between the wires.
Preferably, in the second semiconductor integrated circuit device, the circuit elements are bit cells in a memory device and an area occupied by each of the bit cells is determined by any of the plurality of minimum size values.
Preferably, in the second semiconductor integrated circuit device, the circuit elements are contained in an element formation layer and the wires are contained in a wiring layer, the device further comprising: one or more contacts for providing an electric connection between the element formation layer and the wiring layer, the minimum size value of the finished size of each of the contacts depending on an area occupied by the contact on the substrate or on the number of the contacts.
A third semiconductor integrated circuit device according to the present invention comprises: a design pattern composed of a plurality of circuit elements or the wires formed on a substrate, the design pattern having a plurality of minimum size values in a spacing between parts at different potentials during standby which differ depending on an electric specification and a designing means for implementing the electric specification.
In the third semiconductor integrated circuit device, design margins for the plurality of design patterns are not uniform so that an improvement in the performance of the device is not suppressed by a margin for patterning variations.
Preferably, in the third semiconductor integrated circuit device, the parts at different potentials during standby are formed in different layers.
Preferably, in the second or third semiconductor integrated circuit device, the electric specification is suppression of a leakage current and the designing means includes at least one of power voltage control, power shutdown control, threshold voltage control, and gate-to-source potential control.
Preferably, in the second or third semiconductor integrated circuit device, the electric specification is an operating speed and the designing means includes at least one of power voltage control, threshold voltage control, and delay control effected by using variations in the number of wiring layers used in a layout.
Preferably, in the second or third semiconductor integrated circuit device, the electric specification is a timing value and the designing means includes at least one of selection of synchronous design or asynchronous design, delay control effected by using variations in the number of wiring layers used in a layout, a delay circuit for timing adjustment, a gate size of a transistor, and a layout for adjusting a distance from a clock driver.
Preferably, in the second or third semiconductor integrated circuit device, the circuit elements are memory elements and the designing means is a means for imparting a redundancy function for saving a defect.
A fourth semiconductor integrated circuit device according to the present invention comprises: a plurality of design patterns composed of circuit elements or wires formed on a substrate, the plurality of design patterns having a plurality of minimum size values which differ from one design pattern to another depending on different required specifications dependent on usage modes thereof.
In the fourth semiconductor integrated circuit device, design margins for the plurality of design patterns are not uniform so that an improvement in the performance of the device is not suppressed by a margin for patterning variations.
Preferably, in the fourth semiconductor integrated circuit device, the circuit elements are composed of a plurality of memory elements and the usage modes and the required specifications are set to tolerate a fault in some of the plurality of memory elements.
Preferably, in the fourth semiconductor integrated circuit device, the circuit elements are memory elements and the usage modes and the required specifications are such that the memory elements do not retain data during standby.
A first method for designing a semiconductor integrated circuit device according to the present invention comprises the step of: forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein a plurality of design rules having different values are applied to the plurality of design patterns by using dependence of respective finished sizes of the design patterns on a geometric feature of each of the design patterns.
In accordance with the first method for designing a semiconductor integrated circuit device, design margins for the plurality of design patterns are not uniform so that an improvement in the performance of the device is not suppressed by a margin for patterning variations.
Preferably, in the first method for designing a semiconductor integrated circuit device, the plurality of design rules are applied to a length or width of each of parts composing the circuit elements, a spacing between the parts, an overlapping portion between the parts, or a configuration of a protruding portion of the part and are applied to a width of each of the wires or a spacing between the wires.
Preferably, in the first method for designing a semiconductor integrated circuit device, the circuit elements are bit cells in a memory device and an area occupied by each of the bit cells is determined by any of the plurality of design rules.
Preferably, the first method for designing a semiconductor integrated circuit device further comprises the step of: forming one or more contacts for providing electric connections between the circuit elements and the wires, wherein any of the plurality of design rules is applied by using dependence of the finished size of each of the contacts on an area occupied by the contact on the substrate or on the number of the contacts.
Preferably, in the first method for designing a semiconductor integrated circuit device, the geometric feature is directions or positions of the circuit elements or the wires on the substrate and the plurality of design rules are set to correct dependence of the finished sizes on the directions or positions on the substrate.
Preferably, in the first method for designing a semiconductor integrated circuit device, the geometric feature is a layout density of the circuit elements or the wires on the substrate and the design rules are set to correct dependence of the finished sizes on the layout density.
Preferably, in the first method for designing a semiconductor integrated circuit device, the circuit elements are bit cells in a memory device, the geometric features is a layout type of the bit cells, and the plurality of design rules are set to correct dependence of the finished size on a relationship between a direction in which a gate of a drive transistor extends and a direction in which a gate of an access transistor connected to a word line extends in each of the bit cells.
Preferably, in the first method for designing a semiconductor integrated circuit device, the geometric feature is the presence or absence of a dummy pattern which is a dummy of each of the design patterns contained therein and, if the dummy patterns are contained in the design pattern, the design rules are set to correct dependence of the finished size on the dummy pattern.
A second method for designing a semiconductor integrated circuit device according to the present invention comprises the step of: forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein a plurality of design rules having different values are applied to the plurality of design patterns depending on different finished sizes resulting from an electric specification of each of the design patterns and a designing method for implementing the electric specification.
In accordance with the second method for designing a semiconductor integrated circuit device, design margins for the plurality of design patterns are not uniform so that an improvement in the performance of the device is not suppressed by a margin for patterning variations.
Preferably, in the second method for designing a semiconductor integrated circuit device, the plurality of design rules are applied to a length or width of each of parts composing the circuit elements, a spacing between the parts, an overlapping portion between the parts, or a configuration of a protruding portion of the part and are applied to a width of each of the wires or a spacing between the wires.
Preferably, in the second method for designing a semiconductor integrated circuit device, the circuit elements are bit cells in a memory device and an area occupied by each of the bit cells is determined by any of the plurality of design rules.
Preferably, the second method for designing a semiconductor integrated circuit device further comprises the step of: forming one or more contacts for providing electric connections between the circuit elements and the wires, wherein any of the plurality of design rules is applied by using dependence of the finished size of each of the contacts on an area occupied by the contact on the substrate or on the number of the contacts.
A third method for designing a semiconductor integrated circuit device according to the present invention comprises the step of: forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein the plurality of design patterns include a spacing between parts at different potentials during standby and a plurality of design rules are applied to the plurality of design patterns depending on an electric specification of each of the design patterns and a designing method for implementing the electric specification.
In accordance with the third method for designing a semiconductor integrated circuit device, design margins for the plurality of design patterns are not uniform so that an improvement in the performance of the device is not suppressed by a margin for patterning variations.
Preferably, in the third method for designing a semiconductor integrated circuit device, the parts at different potentials during standby are formed in different layers.
Preferably, in the second or third method for designing a semiconductor integrated circuit device, the electric specification is suppression of a leakage current and the designing method includes at least one of power voltage control, power shutdown control, threshold voltage control, and gate-to-source potential control.
Preferably, in the second or third method for designing a semiconductor integrated circuit device, the electric specification is an operating speed and the designing method includes at least one of power voltage control, threshold voltage control, and delay control effected by using variations in the number of wiring layers used in a layout.
Preferably, in the second or third method for designing a semiconductor integrated circuit device, the electric specification is a timing value and the designing method includes at least one of selection of synchronous design or asynchronous design, delay control effected by using variations in the number of wiring layers used in a layout, a delay circuit for timing adjustment, a gate size of a transistor, and a layout for adjusting a distance from a clock driver.
Preferably, in the second or third method for designing a semiconductor integrated circuit device, the circuit elements are memory elements and the designing method is a method for imparting a redundancy function for saving a defect.
A fourth method for designing a semiconductor integrated circuit device according to the present invention comprises the step of: forming, on a substrate, a plurality of design patterns composed of circuit elements or wires, wherein a plurality of design rules having different values are applied to the plurality of design patterns depending on different required specifications dependent on respective usage modes of the design patterns.
In accordance with the fourth method for designing a semiconductor integrated circuit device, design margins for the plurality of design patterns are not uniform so that an improvement in the performance of the device is not suppressed by a margin for patterning variations.
Preferably, in the fourth method for designing a semiconductor integrated circuit device, the circuit elements are composed of a plurality of memory elements and the usage modes and the required specifications are set to tolerate a fault in some of the plurality of memory elements.
Preferably, in the fourth method for designing a semiconductor integrated circuit device, the circuit elements are memory elements and the usage modes and the required specifications are set such that the memory elements do not retain data during standby.